10nm Chips Promise Lower Costs

The challenges in the supply chain logistics for semiconductors continue to increase, but the 10nm node will give one more opportunity to gain large benefits from technology scaling.

In March 2012, International Business Strategies (IBS) projected that gate costs at 20nm and 16/14nm would be higher than previous generations of technology. The analysis of the gate cost for 10nm now exhibits a different pattern, shown in the figure below.

Handel Jones - Cost per Gates for 10nm
After two nodes of increases, gates prices are expected to decline at 10nm.

While IBS did not project that scaling would stop, it predicted that cost penalties will occur with the adoption of 20nm bulk CMOS HKMG and 16/14nm FinFETs. These predictions on gate cost have been shown to be correct, and while 20nm products are in high volume for Apple, wafer capacity at 20nm is much lower than at 28nm.

TSMC provides another example. Its wafer capacity at 28nm is 150,000 wafers per month (WPM), but its wafer capacity at 20nm is nearly a third as much – 60,000 WPM. Globalfoundries also has 20nm capacity in its Malta, New York fab but the primary emphasis of this facility is on FinFETs. As for Samsung Electronics and UMC, they have decided to bypass 20nm.

While 16/14nm wafer volumes are ramping, wafer capacity at 16/14nm is again lower than 28nm. The wafer volume at 16/14nm is also driven by Apple again, but the length of use for 16/14nm technology will be determined by how rapidly 10nm will occur.

The lower gate cost at 10nm is due to the higher gate density that can be obtained compared to the increase in wafer cost. To attain lower gate cost at 10nm, there will be the need for high systemic and parametric yields, but this is achievable.

The expectation is that 10nm will be a high volume and long lifetime technology node. TSMC and Samsung are projecting risk production for 10nm in Q4/2015, and the customer target is clearly Apple. If there is the ability to ramp up 10nm in 2016 or even in mid-2017, 16/14nm will be a short lifetime technology node.

The capital expenditure required for 10nm, however, is approximately $2 billion for 10,000 WPM, and a facility running 40,000 WPM will cost $8 billion. Also, the minimum cost for a design at 10nm will be $150 million, so if revenues for a chip need to be ten times higher than design costs to get a good return on the investment, 10nm chips will need to achieve sales of $1.5 billion.

After 10nm, there will likely be the need for extreme ultraviolet (EUV) technology, and there is steady progress on enhancing EUV throughput. While 450mm wafer technology continues to be worked on, its introduction will not likely occur before 2020.
 
 
Handel Jones is founder and CEO of International Business Strategies Inc., which provides custom studies in multiple areas of the electronics industry.

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3 Responses to 10nm Chips Promise Lower Costs

  1. mtlin says:

    這位 Handel Jones 於 Day 2 of SEMI’s Industry Strategy Symposium (ISS) 2012 上的預測:

    Handel Jones, Founder of IBS, forecast some high level IC trends for the next 5 years. We will continue the trend of a 10x increase in wireless bandwidth every 5 years. Demand is strong but delivery is lagging for 28nm HKMG devices; 20nm is expected to ramp even more slowly. Intel is thought to be 18-30 months ahead of the industry in FinFET implementation. Declarations of insolvency are expected for several DRAM manufacturers, which he declined to identify. The projected cost per gate is increasing slightly at 22nm and 14nm, a trend that must be reversed. IC revenue growth will be low as fabs lower prices to protect market share in an unstable global economy. Qualcomm will be a $30B fabless company in 2015. Samsung will challenge Intel for the position of largest semiconductor manufacturer. TSV must reduce cost and stress problems in order to become competitive. 3D packaging can provide a competitive advantage equivalent to a half node.

    Cost per Million Gates - 2012

  2. mtlin says:

    2014 年,同一位 Handel Jones 先生的預測:

    Cost per Gate Trend with Reduction in Feature Dimensions

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