PARIS – Subject to time-to-market factors, Spreadtrum Communications Ltd. (Shanghai, China) has adopted Cadence’s Silicon Realization products for the design of a 40-nm low power TD-HSPA/TD-SCDMA multi-mode communication baseband processor. The chip was taped out with one-pass silicon success and is commercially available in China.
Designed with 40-nm CMOS silicon technology, Spreadtrum said the SC8800G chip enables TD-HSUPA, TD-SCDMA, GSM, GPRS and EDGE operation and supports TD-HSDPA at 2.8Mbps, TD-HSUPA at 2.2Mbps. It is claimed to achieve groundbreaking levels of performance and integration while simultaneously reducing power consumption, lowering overall costs and meeting the need for next generation communication experience.
The history behind this announcement is that Spreadtrum migrated to the Cadence Silicon Realization flow and taped out its first 40-nm low-power chip with one-pass silicon success. By adopting Cadence-centric Silicon Realization solutions, Charlie Huang (see photo), senior vice president and chief strategy officer at Cadence Design Systems Inc., explained to EE Times that Spreadtrum gained the advantages of time to market.
Cadence presents Silicon Realization as a novel approach to semiconductor design, verification and implementation. It extends traditional EDA to cover both integration and creation. It unites functional, physical and electrical concerns. It is based on three requirements for a deterministic path to silicon: unified design intent, design abstraction and design convergence.
Part of Cadence‘s EDA360 initiative for application-driven design, Silicon Realization is claimed to cover the entire scope of tools and capabilities required to get a design into silicon – be it analog or digital IP block, an IP subsystem for a SoC or a completed IC or SoC – including the package in which the silicon sits.
Among the Cadence-centric Silicon Realization tools, Spreadtrum said it has adopted Encounter Digital Implementation System, RTL Compiler, Conformal Low Power, Incisive Enterprise Simulator, Encounter Test, Encounter Timing System, Virtuoso Custom Design, Multi-mode Simulation, QRC Extraction, Encounter Power System and design-for-manufacturing technologies.
Huang outlined that this collaborative development is significant on many fronts.
Firstly, he outlined that this is the first publicly announced 3G mobile baseband chip at 40-nm in China, and one of the first few in the world. Secondly, the design was done in substantially an all-Cadence low-power implementation flow, demonstrating the capabilities of the solution.
Third point: Huang noted that Spreadtrum design team’s prior design was created for a 150nm process, using another EDA company’s tools. This means that Spreadtrum performed a giant leap over multiple nodes and simultaneously changed to a substantially all-Cadence design flow. “This kind of transition is possible only with established trust and solid collaboration between us,” he stated.
Finally, Huang specified that the design did not go through the usual steps of shuttle and metal fixes but came back working the first time in good yield in production volume, which demonstrates the strength of Cadence‘s solution from design through verification to DFM.
The chip, a GSM/GPRS/EDGE/TD-SCDMA/HSPA mobile phone baseband, was taped out in September 2010, came back in October, and the system was subsequently brought up, validated and certified by cell phone makers, testing labs and mobile carriers in the past few weeks, Huang explained.
He commented: “I have in my hand a working 3G phone by Huawei, commercially available in China that uses the Spreadtrum chip. Several other cell phone vendors have also put out model containing this chip.”
Huang indicated that there have been many close collaborations between Cadence and Spreadtrum. However, he continued, “this is a very substantial and ambitious undertaking, made possible with great vision match by our respective CEOs and confidence and trust by Spreadtrum in Cadence through prior interactions.”
Currently, the two companies are actively working on several similarly large-scale collaborations, Huang said.
In recent months, other companies have adopted the Silicon Realization approach. Open Silicon indeed claimed it had successfully taped out a high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence Silicon Realization product line.
Similarly, SMIC adopted Cadence Silicon Realization products for the design-for-manufacturing (DFM) and low-power technology at the core of SMIC’s 65-nanometer Reference Flow 4.1. The Chinese foundry then claimed significant productivity boost.
Anne-Françoise PELE, EETimes